The present invention pertains to memories in data processing equipment.
Many different types of data processing equipment are manufactured and used in the present day market, such as microprocessors, micro controllers, digital signal processors (DSP), or the like. All of these types of data processing equipment use a variety of memories, such as a data memory, a program or instruction memory, a boot memory, a cache memory, controlling shift registers, etc. At the present time, all of these various memories use memory devices such as DRAMs, SRAMs, flash memories, ROMs, PROMs, etc. For example, data and program memories typically use SRAMs, ROMs, or flash memories for the storage of data and operating programs. While SRAMs are very high speed, they are volatile, which means that they loose the data when power is removed and, therefore, their use is very limited. Other types of memories are generally slower and many of them require much additional circuitry, which renders them costly and relatively large.
It would be desirable, therefore, to provide data processing equipment which overcomes these drawbacks.
It is an object of the present invention to provide new and improved memories in data processing equipment.
It is another object of the present invention to provide new and improved memories in data processing equipment which is as fast as SRAMs but non-volatile.
It is still another object of the present invention to provide new and improved memories in data processing equipment with dual read ports to further enhance the speed of the equipment.
The above problems and others are at least partially solved and the above objects and others are realized in processing equipment with embedded MRAMs and a method of fabricating the equipment. The data processing equipment includes a data processing device fabricated on a semiconductor chip with MRAM cells fabricated on the chip to form one to all of the memories on the chip, including a data memory, a program or instruction memory, a boot memory, a cache memory, and controlling shift registers in communication with the data processing device.
Also, in a specific embodiment, the data processing equipment includes a dual bank memory in communication with the data processing device and circuitry coupled to the data processing device and the dual bank memory for providing simultaneous read access to the dual bank memory.